1. Field of the Invention
The present invention relates to a microelectronic device, and, more particularly, to a method of fabricating interconnections of a microelectronic device using a dual damascene process.
2. Description of the Related Art
In general, metal interconnections are used to connect a microelectronic device to another device and connect an interconnection to another interconnection.
Aluminum or tungsten is widely used as the material of metal interconnections, but, due to a low melting point and a high resistivity, is no longer suitable for highly integrated semiconductor devices. As the integration density of microelectronic devices, for example, semiconductor devices, increases, the demand for a material which has a low resistivity and is highly reliable in terms of electromigration and stress migration has steadily grown, and recently more attention has been paid to copper as a suitable material for metal interconnections of highly integrated semiconductor devices.
Copper is deemed suitable for metal interconnections because it has a relatively high melting point of approximately 1080° C. (aluminum: 660° C., tungsten: 3400° C.) and a relatively low resistivity of 1.7 μΩcm (aluminum: 2.7 μΩcm, tungsten: 5.6 μΩcm).
A copper interconnection fabrication method involves a complicated and difficult etching operation and may suffer from erosion diffusion. Thus, it is difficult to put a copper interconnection fabrication method to practical use.
In order to address these problems, a single damascene process and a dual damascene process have been used. In a damascene process, a trench or a via is formed by patterning a dielectric layer using photolithography, the trench or the via is filled with a conductive material such as tungsten, aluminum, or copper, and an excessive conductive material is removed using etch-back or chemical vapor deposition (CVD), thereby forming an interconnection that conforms the shape of the trench or the via.
However, as the design rule of the interconnection becomes more constrained, during a dual damascene process, the filling margin of a conductive material unavoidably increases. Accordingly, there is a need for a reliable dual damascene process capable of fabricating a flawless dual damascene interconnection by increasing the filling margin of a conductive material.